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ds04-13106-2e fujitsu semiconductor data sheet linear ic converter cmos a/d converter (with 24-channel input at 10-bit resolution) mb88111 n description the mb88111 is an analog-to-digital converter that converts its analog input to a 10-bit digital value and outputs it as serial data. the mb88111 employs a successive approximation method for a/d conversion. it has 24 input channels to be a/ d converted selectively by setting in an internal register. since the mb88111 can input and output 16-bit serial data in synchronization with the clock, it can be easily connected to the serial i/o port in a 16-bit microcontroller. n features ? 24-channel analog input ? rc-type successive approximation system with a sample-and-hole circuit ? 10-bit resolution ? conversion speed within 50 m s (at a system clock rate of 1 mhz) ? digitally converted data output from the msb ? digitally converted data output as 16-bit serial data ? clock-synchronous serial transfer system ? internal extended serial interface ? capable of triggering a/d conversion through an external pin ? capable of input through an 8-channel port ? serial data output format selectable using an external pin ? 10-bit monotonicity ? no missing code ? power supply voltage ranging from 3.5 to 5.5 v (continued) n pac k ag e s (dip-48p-m01) 48 pin, plastic sh-dip 44-pin, plastic qfp (fpt-44p-m11)
2 mb88111 (continued) ? operating temperature ranging from C40 to +50 c ? cmos process ? package options of 44-pin qfp and 48-pin sh-dip n pin assignment (continued) an7 an6 an5 an4 an3 an2 an1 an0 avrh av cc v cc an19 an20 an21 an22 an23 agnd avrl v ss testi n.c. mod rstx sck cclk sin esin sot endc irqx atgx cs2x cs1 an8 an9 an10 an11 an12 an13 an14 an15 an16 an17 an18 (top view) index (fpt-44p-m11) 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 1234567891011 33 32 31 30 29 28 27 26 25 24 23
3 mb8 8 111 ( c o n tinue d ) an1 an0 avrh av cc v cc n.c. rstx sck cclk sin esin sot endc irqx atgx cs2x cs1 n.c. mod n.c. testi v ss avrl an2 an3 an4 an5 an6 an7 n.c. an8 an9 an10 an11 an12 an13 an14 an15 an16 an17 an18 n.c. an19 an20 an21 an22 an23 agnd index ( top view ) ( dip-48p-m01 ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
4 mb88111 n pin description (continued) pin no. symbol i/o circuit type descriptions qfp dip 41 to 26 2 to 1, 48 to 43, 41 to 34 an0 to an15 i f analog input pins. the pin to be subject to conversion is selected by the command input through the sin pin. also, a series of pins from an16 to an23 can be used as a port input. 25 to 18 33 to 31, 29 to 25 an16 to an23 g 12 19 mod i a pin for selecting a serial data output mode: l: mode a for output from the sot pin in synchronization with the fall of the sck signal. h: mode b for output from the sot pin in synchronization with the rise of the sck signal. 11 10 17 16 cs1 cs2x i a input pins for selecting an extended serial interface mode. setting the cs1 level to h and the cs2x level to l enables a/d converted data transfer. setting the cs1 level to l or the cs2x level to h clears the register command without affecting a/d conversion. serial data input to the external extended serial input pin esin is output to the sot pin as it is. (see section 7 extended serial interface in n operation.) 4 10 sin i b serial data input pin this pin is a hysteresis input with a filter. 6 12 sot o h serial data output pin 3 9 cclk i b system clock input pin this pin is a hysteresis input. 2 8 sck i b serial data transfer clock input pin this pin is a hysteresis input with a filter. 9 15 atgx i c external trigger input pin. this pin incorporates a pull- up resistor. the atc command initiates a/d conversion at the rise of the signal at this pin. the pin is a hysteresis input. 8 14 irqx o h a/d conversion interrupt signal input pin. the signal level becomes l upon completion of a/d conversion; it becomes h upon reception of data to be converted. 7 13 endc o h a/d conversion completion signal output pin. the signal level becomes h upon completion of a/d conversion; it becomes l upon reception of data to be converted. 5 11 esin i a serial input extension input pin. when the cs1 level is l or the cs2x level is h, data input to the esin pin is output to the sot pin as it is. 1 7 rstx i d reset signal input pin. this pin incorporates a pull-up resistor. setting the signal level to l initializes the internal circuit of the device. this pin is a hysteresis input with a filter.
5 mb88111 (continued) n i/o circuit type (continued) pin no. symbol i/o circuit type descriptions qfp dip 14 21 testi i e test input pin. this pin incorporates a pull-down resistor. maintain the pin at l level during normal use. 44 5 v cc digital circuit power supply pin 15 22 v ss digital circuit ground pin 43 4 av cc analog circuit power supply pin 17 24 agnd analog circuit ground pin 42 3 avrh reference (high) voltage input pin 16 23 avrl reference (low) voltage input pin 13 6, 18, 20, 30, 42 n.c. non-connection pin type circuit remarks a ? cmos input b ? hysteresis input ? cmos input c ? input with pull-up resistor ? cmos input
6 mb88111 (continued) type circuit remarks d ? input with pull-up resistor ? hysteresis input ? cmos input e ? input with pull-down resistor ? cmos input f ? analog input g ? analog input ? hysteresis input ? cmos input h ? cmos output
7 mb88111 n block diagram an0 an15 an16 atgx sck esin sin mod cs2x cs1 rstx testi cclk v cc v ss sot irqx endc av cc agnd avrh avrl multiplexer port input sample-and-hold circuit comparator 10-bit d/a converter successive approximation register control circuit command register data register output select circuit interface control circuit an23
8 mb88111 n functional description 1. sc (serial command) register (reset status: 0000h) the sc register contains an a/d converter command and an input channel identification. accessing this register after releasing it from the reset status activates the a/d converter. note that this register accepts setting even during a/d conversion. note also that input of a command to the register must take an interval of at least 4 cclks after input of the previous command. (1) command bits a string of command bits selects an a/d converter command such as stop. setting a command during execution of another command cancels the command currently being executed. * : these command settings cause the stop command to be executed. bf be bd command name function 000 stop stops a/d conversion (if it is being executed) and initializes the a/d converter. this command has the same effect as rstx. 001 stc executes a/d conversion of the specified channel once. (see section 3 stc (standard conversion) command.) 0 1 0 unused (*) 0 1 1 unused (*) 100 nop no-op command. input of this command during a/d conversion does not affect operation. if followed by this command, the atc command can transfer converted data while holding the nop command. 101 atc the basic operation of this command is the same as that of the stc command. the atc command can leave the a/d conversion start timing to the external trigger pin atgx. (see section 4 atc (auto trigger conversion) command.) 1 1 0 unused (*) 1 1 1 unused (*) bf be bd bc bb ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 msb command lsb don't care channel
9 mb88111 (2) channel select bits a string of channel select bits selects the pin to be subject to a/d conversion. this bit string is enabled only for the stc or atc command. *1: these settings of the bit string cause the stop command to be executed. *2: this setting is enabled only for the stc command. (see section 5 port input command.) if this setting is made for the atc command, the stop command is executed. 2. data output format upon completion of a/d conversion, the endc pin level becomes h and the irqx pin level becomes l. execution of serial transfer at this time outputs data in the format illustrated below. the data output timing can be selected by the mod pin between the falling edge (mode a) or rising edge (mode b) of the sck signal. when the endc pin level is l, 0000h is output. endc (a/d conversion completion flag): this bit is set to 1 upon completion of a/d conversion. it is set to 0 upon completion of serial transfer. note: sck input upon low-to-high transition of the endc pin level should be avoided. otherwise, data may not be output correctly. bc bb ba b9 b8 pin to be selected bc bb ba b9 b8 pin to be selected 00000 an0 10000 an16 00001 an1 00010 an2 10111 an23 00011 an3 11000 undefined (*1) 00100 an4 11001 11010 01011 an11 11011 01100 an12 11100 01101 an13 11101 01110 an14 11110 01111 an15 11111 port input an16 to an23 (*2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bf be bd bc bb ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 msb lsb endc a/d converted pin converted data
10 mb88111 3. stc (standard conversion) command input of the stc command executes a/d conversion of the specified channel once. impletion of a/d conversion, the endc signal rises while the irqx signal falls. clock input to the sck pin after a/d conversion outputs data to the sot pin. upon completion of data output, the endc signal falls while the irqx signal rises. if the next command is stop or nop, the a/d conversion is terminated. if the stc command is input during a/d conversion, the command currently being executed is cancelled and the stc command is executed. ? example of stc command execution (1) stc command input during a/d conversion cancels the current command and executes a/d conversion of the new specified channel. output data at this time is 0000h. ? example of stc command execution (2) nop command input during a/d conversion does not affect operation. output data at this time is 0000h. if a/ d conversion is completed during nop command input, the endc and irqx pin levels become h and l respectively upon completion of the nop command input. sck sin sot endc irqx a/d 16 cycle an0 0000h an1 data 0 an2 0000h stop data 2 an0 conversion an1 conversion an2 conversion sck sin sot endc irqx a/d 16 cycle an3 0000h nop 0000h nop data 3 an4 0000h nop 0000h stop data 4 an3 conversion an4 conversion
11 mb88111 4. atc (auto trigger conversion) command the atc command is the same as the stc command in basic operation. this command can initiates a/d conversion using the external trigger pin atgx. the external trigger signal is sampled by 1 m s clock and filtered by 1 clock. the external trigger signal input during a/d conversion is ignored. if the next command is the stop command, a/d conversion is terminated. if it is the nop command, the atc command is executed continuously. the channel cannot be changed at this time. to change the channel, input the atc command to that effect. ? example of atc command execution (1) nop command input during a/d conversion enables the same channel to be a/d converted. an attempt to set the atgx signal low during a/d conversion is ignored. nop command input during a/d conversion does not affect operation. output data at this time is 0000h. ? example of atc command execution (2) setting the atgx signal low again after a/d conversion restarts a/d conversion. in data output mode b, however, do not use the atc command in this way, or data will not be output correctly. if a/d conversion is completed during nop command input, the endc and irqx pin levels become h and l respectively upon completion of the nop command input. sck sin sot endc irqx a/d atgx 16 cycle an5 nop an6 nop stop 0000h data 5 data 5 0000h data 6 an5 conversion an5 conversion an6 conversion sck sin sot endc irqx a/d atgx 16 cycle an7 0000h an8 data 7 nop stop 0000h data 8 an7 conversion an7 conversion an8 conversion an7 conversion
12 mb88111 5. port input command the port input command executes i/o evaluation of 8-channel inputs from the an16 to an23 pins at a prescribed threshold in 10 clock cycles and outputs the results as port input data. the processing sequence is activated each time port input is selected by the stc command. port input data is output in the following format: evaluation data: the evaluation values of an23 to an16 are output to bits bf to b8. evaluation value h: vin 3 0.8 x vcc l: vin 0.2 x vcc endc (a/d completion flag): this bit is set to 1 upon completion of a/d conversion. it is set to 0 upon completion of serial transfer. ? example of stc command execution (3) (port input command) bf be bd bc bb ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 msb lsb endc ? evaluation data ? sck sin sot endc irqx an16 to an23 a/d 16 cycle 10 cycle 16 cycle stop 0000h ch9 data 9 evaluation
13 mb88111 6. serial output select function the mb88111 can select the serial data output timing between the rising edge or falling edge of the clock signal according to the setting of the mod pin. 7. extended serial interface the mb88111 can select whether to output a/d converted data or to output data input to the esin pin by controlling the cs1 and cs2x pins. note: a/d converted data is not guaranteed if the cs1 or cs2x setting is changed during sck input. cs1 cs2x sot pin h l a/d converted data ll connection to the esin pin lh hh sck sot sin msb msb lsb lsb bf be bd bc ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 bb bf be bd bc ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 bb bf be bd bc ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 bb bf be bd bc ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 bb sck sot sin msb msb lsb lsb note: a/d converted data is not guaranteed if the mod pin is switched when the endc signal is active. before changing the output mode, make the endc inactive or set the rstx pin level to l after switching the mod pin. mode a (mod = l) serial data is output at the falling edge of the sck signal. note: a/d converted data is not guaranteed if the mod pin is switched when the endc signal is active. before changing the output mode, make the endc inactive or set the rstx pin level to l after switching the mod pin. the first bit is output when the endc signal becomes h. mode b (mod = h) serial data is output at the rising edge of the sck signal.
14 mb88111 n electrical characteristics 1. absolute maximum ratings (v ss = agnd = 0 v) * : v cc 3 av cc 3 avrh 2. recommended operating conditions * : v cc 3 av cc 3 avrh parameter symbol conditions ratings unit min. max. power supply voltage v cc based on v ss (ta = +25 c) C0.3 +7.0 v av cc C0.3 +7.0* v avrh C0.3 +7.0* v input voltage v in C0.3 v cc + 0.3 v output voltage v out C0.3 v cc + 0.3 v power consumption p d 150 mw storage temperature t stg C55+150 c parameter symbol values unit min. max. power supply voltage v cc av cc 3.5* 5.5* v v cc agnd 00v avrh av cc 0.8 av cc v avrl 0 av cc 0.2 v operation temperature ta C40 +105 c
15 mb88111 3. dc characteristics (1) digital section (v cc = +3.5 v to +5.5 v, v ss = agnd = 0 v, ta = C40 c to +105 c) * : an16 to an23 (port input mode) parameter pin name symbol conditions value unit min. typ. max. power supply voltage v cc v cc 3.5 5.0 5.5 v power supply current i cc operation at clk = 1 mhz (with no load) 0.51.5ma low-level input leakage current mod, cclk cs1, cs2x sck, esin sin i izl1 v in = v ss C2 2 m a at g x rstx i izl2 v in = v ss v cc = 5.0 v C200 C100 C50 m a high-level input leakage current mod, cclk cs1, cs2x sck, esin sin, atgx rstx i izl1 v in = v cc C2 2 m a low-level input voltage mod, esin cs1, cs2x v il v ss - 0.3 0.3 v cc v sck, cclk sin, atgx rstx, * v ils v ss - 0.3 0.2 v cc v high-level input voltage mod, esin cs1, cs2x v ih 0.7 v cc v cc + 0.3 v sck, cclk sin, atgx rstx, * v ihs 0.8 v cc v cc + 0.3 v hysteresis width sck, cclk sin, atgx rstx, * v hys 0.02 v cc 0.3 v cc v low-level output voltage sot irqx endc v ol i ol = 2.5 ma 0.4 v high-level output voltage v oh i oh = C400 m av cc - 0.4 v
16 mb88111 (2) analog section (av cc , v cc = +3.5 v to +5.5 v (v cc 3 av cc ), v ss = agnd = 0 v, ta = C40 c to +105 c) ? no missing code is guaranteed. notes: if the output impedance of the external input is too high, the analog voltage sampling time may be insufficient. in the power-on sequence, turn the power supply for the digital system first before turning that for the analog system on. parameter pin name symbol conditions value unit min. typ. max. resolution an0 to an23 10bits monotonic increase 10 bits linearity error 1lsb differential linearity error 1lsb full-scale transition error 1/2 lsb zero-transition error 1/2 lsb total error 2lsb conversion time cclk = 1 mhz 50 m s input clock frequency cclk 800 1000 1200 khz supply current av cc ia 3.0 6.0 ma reference voltage supply current avrh ir 150 300 m a analog reference voltage avrh 0.8 av cc av cc v avrl 0 0.2 av cc v analog input voltage an0 to an23 avrl avrh v multiplexer off-leakage current C200 200 na analog input equivalent circuit analog input r on1 c 0 r on2 comparator r on1 = about 1.5 k w r on2 = about 1.5 k w c 0 = about 15 pf note: the above values are reference values.
17 mb88111 4. ac characteristics (av cc , v cc = +3.5 v to +5.5 v (v cc 3 av cc ), v ss = agnd = 0 v, ta = C40 c to +105 c) parameter symbol conditions values unit min. max. cclk clock cycle time f clk f clk = 1/f clk 800 1200 khz low-level cclk clock pulse width t ckl 400ns high-level cclk clock pulse width t ckh 400ns cclk clock rise time t cr C10ns cclk clock fall time t cf sck clock cycle time f sck t sck = 1/f sck 400 1200 khz low-level sck clock pulse width t skl 400ns high-level sck clock pulse width t skh 400ns sck clock rise time t sr C10ns sck clock fall time t sf sin setup time t sis 50ns sin hold time t sih 250ns command interval t com cclk = 1 mhz 4 m s endc reset time t enr see load conditions. C 1 m s rstx pulse width t rsh 100ns rstx - ? sck time t rss 1 m s sck - ? cs1 time sck - ? cs2x - time t css 500ns cs1 - ? sck time cs2x ? sck time t csh 500ns sot output delay time (mode a) t soda see load conditions. 300 ns sot output delay time (mode b) t sodb see load conditions. 300 ns endc - ? sot output (mode b) t sohb see load conditions. 200 ns stc command a/d conversion time t stc cclk = 1 mhz 50 m s atc command a/d conversion time t satc cclk = 1 mhz 50 m s atgx setup time t sats cclk = 1 mhz 4 m s atgx hold time t sath cclk = 1 mhz 2 m s port input evaluation time t pot cclk = 1 mhz 10 m s port input setup time t pts 0ns port input hold time t pth 0ns extended serial hl propagation delay t shl see load conditions. 100 ns extended serial lh propagation delay t slh see load conditions. 100 ns noise filter width t inf 15ns
18 mb88111 n timing diagram 1. input clock timing measurement point c l = 50 pf a c t es t cond i t i on cclk sck t clk t ckh t cf t ckl t cr t sck t skh t sf t skl t sr e v al u at i on l e v e l s a r e 8 0 % an d 20 % of t h e v c c .
19 mb88111 2 . ser i al data i nput tim i ng 3 . ser i al data outpu t t i ming rstx sck cs1 sin endc b0 bf be t rsh t rss t com t css t csh t sis t sih t enr ( cs2x ) e v al u at i on l e v e l s a r e 8 0 % an d 20 % of t h e v c c . sck sot sck sot endc t soda t sodb t sohb bf be bf be evaluation levels are 80% and 20% of the v cc . evaluation levels are 80% and 20% of the v cc . mode a mode b
20 mb88111 4. a/d conversion and port input evaluation evaluation levels are 80% and 20% of the v cc . evaluation levels are 80% and 20% of the v cc . stc command (normal mode) atc command sck sin endc b0 t stc sck sin atgx endc b0 t ats t ath t atc
21 mb88111 5. extended serial interface 6. noise filter sck sot an16 endc b0 t pts t pot t pth to an23 evaluation levels are 80% and 20% of the v cc . stc command (port input mode) evaluation levels are 80% and 20% of the v cc . esin sot t shl t slh evaluation levels are 80% and 20% of the v cc . t inf t inf
22 mb88111 n definitions of a/d converter terms ? resolution analog transition identifiable by the a/d converter ?linearity error deviation of the straight line drawn between the zero transition point (00 0000 0000 ? 00 0000 0001) and the full-scale transition point (11 1111 1110 ? 11 1111 1111) of the device from actual conversion charac- teristics ? differential linearity error deviation from the ideal input voltage required to shift output code by one lsb ? total error difference between actual and logical values. this error is caused by a zero transition error, full-scale transition error, linearity error, quantum error, and by noise. (continued) ideal i/o characteristics 3ff 3fe 3fd 004 003 002 001 v ot 1 lsb (ideal value) (ideal value) v fst (ideal value) 1.5 lsb avrh avrl avrl avrh analog input analog input total error 3ff 3fe 3fd 004 003 002 001 {1 lsb (n?) +0.5 lsb} v nt ' (measured value) actual conversion characteristics ideal characteristics avrh?vrl 1024 [v] [v] [v] v fst (ideal value) = avrh - 1.5 lsb v ot (ideal value) = 0.5 lsb v nt ' ?{1 lsb (n?) +0.5 lsb} 1 lsb 1 lsb (ideal value) = total error of digital output n = 0.5 lsb digital output actual conversion characteristics digital output
23 mb88111 (continued) 004 003 002 001 avrl avrh avrl avrh avrl avrh 3ff 3fe 3fd 3fc n+1 n n - 1 n - 2 3ff 3fe 3fd 004 003 002 001 zero transition error full-scale transition error differential linearity error linearity error v fst ' v ot ' (measured value) (measured value) v fst ' v nt ' v ot ' (measured value) v nt ' v( n + 1)t ' {1 lsb (n?)+v ot ' } v ot ' ?.5 lsb 1 lsb v fst ' ?(avrh?.5 lsb) 1 lsb v nt ' ?{1 lsb ' (n?)+v ot ' } 1 lsb ' v (n+1)t ' ? nt ' 1 lsb ' ? full scale transition error = = linearity error of digital output n = v fst ' ?v ot ' 1022 1 lsb' = [v] actual conversion characteristics actual conversion characteristics ideal characteristics digital output actual conversion characteristics digital output actual conversion characteristics analog input zero transition error = analog input differential linearity error of digital output n (measured value) (measured value) actual conversion characteristics ideal characteristics actual conversion characteristics analog input digital output (measured value) (measured value) actual conversion characteristics ideal characteristics actual conversion characteristics analog input digital output
24 mb88111 n ordering information part number package remarks mb88111pfq 44-pin, plastic qfp (fpt-44p-m11) MB88111P-SH 48-pin, plastic sh-dip (dip-48p-m01)
25 mb88111 n package dimensions "b" (.055.012) 1.400.30 0~10 0.18(.007)max 0.53(.021)max 0.20(.008) 0.15(.006) (.006.002) 0.150.05 "a" sq 10.000.20 (.394.008) sq (.567.016) lead no. 0.80(.0315)typ 44 12 22 34 33 23 111 details of "b" part index 0.10(.004) ref (.315) (.457.012) 8.00 11.600.30 (stand off) 0.05(.002)min 2.35(.093)max m 0.16(.006) (.012.004) 0.300.10 14.400.40 details of "a" part 1994 fujitsu limited f44018s-1c-1 c (mounting height) +0.50 C0 C0 +.020 C.012 +.008 C0.30 +0.20 0.51(.020)min min max 40.894(1.610)ref index-2 15max typ 15.24(.600) (.010.002) 0.250.05 max 1.778(.070) (.070.007) 1.7780.18 1.00 .039 (.018.004) 0.450.10 3.00(.118) 5.25(.207) index-1 (.543.010) 13.800.25 1.720 43.69 1994 fujitsu limited d48002s-3c-3 c dimensions in mm (inches). 44-pin, plastic qfp (fpt-44p-m11) dimensions in mm (inches). 48-pin, plastic sh-dip (dip-48p-m01)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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